Harvard Architecture

The bus architecture modifies the Harvard architecture to provide enough data rate for computing units .

总线结构采用哈佛结构，能够保证DSP有足够的数据吞吐率，为计算部件提供充分的数据；

In the design of the cache controller of Harvard architecture , the 4-way associated mapping algorithm is adopted .

在哈佛结构的cache控制器设计中，映射算法采用4路组相联的映射算法。

Modeling and Simulation of Container Terminal Logistics System Based on Harvard Architecture

基于哈佛体系结构的集装箱码头物流系统建模仿真研究

Design of Cache Controller with Harvard Architecture

哈佛体系结构的Cache控制器设计

In a general purpose DSP which is based on modified harvard architecture , a small instruction cache is adopted to alleviate the resource conflict in the pipeline .

在一款采用改进HARVARD总线结构的通用DSP中，通过设置一个小型指令CACHE来缓解流水线上的资源冲突。

DSP chip is harvard architecture . And it is preferred tool to rapidly accurately deal with digital signal by means of peculiar hardware architecture and load-store .

DSP芯片采用哈佛结构，以独特的硬件体系以及指令体系迅速成为实时数字信号处理的首选工具，强大的数据处理功能使其广泛应用于通信领域。

To archive high performance , DVD servo control microprocessor uses RISC like instruction set . Harvard architecture has been used for the servo control microprocessor , having four program and data buses .

为了获得比较高的性能，设计DVD伺服控制微处理器时，采用了具有RISC特征的指令集，程序和数据总线分离的哈佛结构，内部使用了四条程序和数据总线。

In this thesis , an 8-bit RISC MCU is designed . This system uses a Harvard architecture , in which program and data are accessed from separate memories using separate buses .

本论文所设计的一款8位RISC体系结构的MCU，其主要特点是：采用哈佛体系结构；

The paper also discusses the concept of Harvard architecture , the Virtual Cache , the Physical Cache , " writethrough " mode and " copyback " mode of Data & Cache .

讨论了哈佛结构、虚拟Cache、物理Cache、数据Cache的写通和写回方式等。

The core mends traditional 51 series MCU on structure , instruction system and instruction time . The performance of designed MCU has been greatly improved by adopting Harvard architecture , single-phase clock and synchronous design .

该处理器内核采用哈佛结构、单相时钟、全同步设计，在内核结构、指令系统和指令时序上对传统的51系列MCU进行了改进，从而加快了微处理器的处理速度，提高了指令的执行效率。

TMS320VC5402 is one of the members of C54X family of TI Company , it is a16 fixed DSP based on an advanced modified Harvard architecture that has one program memory bus and three data memory buses .

TMS320VC5402是TI公司的C54X家族的成员之一，它是基于先进的改进哈佛结构的16位定点DSP，拥有一条程序总线和三条数据总线。

The RISC MCU core is based on Harvard architecture with 14-bit instruction length and 8-bit data length and two-level instruction pipeline The performance of the RISC MCU has been improved by replacing micro-program with direct logic block .

设计的RISCMCU采用14位字长指令总线和8位字长数据总线分离的Harvard结构和二级指令流水设计，并使用硬布线逻辑代替微程序控制，加快了微控制器的速度，提高了指令执行效率。

There are six buses in the Harvard memory architecture .

在处理器的超哈佛存储结构中，集成了6条总线对存储器模块进行访问。